1. Field of the Invention
The present invention relates to a manufacturing method for a liquid crystal display device using a selective etching method. More specifically, the present invention relates to an etching method for manufacturing a liquid crystal display having a TFT (thin film transistor), gate bus lines, data bus lines which include a refractory metal such as Mo, Ta, Ti, MoSi, TaSi or TiSi, and a passivation layer covering them, wherein the refractory metal is not damaged by the etchant used for forming the passivation layer.
2. Description of the Background Art
Generally, a thin film type liquid crystal display device includes a lower plate, an upper plate joined to the lower plate, and a liquid crystal disposed therebetween. At the outer portions of the two connected plates, polarizing plates are attached. That is, the upper plate includes an inner side having a color filter and a common electrode, and an outer side having a polarizing plate. The lower plate includes an outer side having a polarizing plate as well, and an inner side having a plurality of gate bus lines 20 and data bus lines 10 arranged perpendicular to and crossing with each other, and a pixel electrode 55 positioned at an inner space defined by the crossed gate bus lines 20 and the data bus lines 10, as shown in FIG. 1. That is, a plurality of the gate bus lines 20 are arranged to extend in a horizontal direction on the lower plate, and gate electrodes 21 are extended from the gate bus lines 20. A plurality of the data bus lines 10 are arranged to extend perpendicularly to the gate bus lines 20 and source electrodes 11 are extended from the data bus lines 10. Drain electrodes 31 facing the source electrodes 11 are disposed so that the TFT switching elements, including the gate electrodes 21, the source electrodes 11 and the drain electrodes 31, are completed.
To drive the LCD, each data bus line 10 is connected to an output of a signal driver IC generating the data signal of the picture, and each gate bus line 20 is connected to a output of a scan driver IC generating the scan signal of the picture.
A process to manufacture the lower plate of the LCD is explained below referring to FIGS. 1 to 4c. FIG. 1 is a plane view showing the lower plate of a conventional liquid crystal display device. FIGS. 2a-2c, 3a-3c, and 4a-4c are cross-sectional views showing a conventional method for etching the passivation layer covering a switching element as denoted by line axe2x80x94a in FIG. 1, a gate pad 22 as denoted by line bxe2x80x94b, and data pad 12 as denoted by line cxe2x80x94c, respectively.
As shown in the figures, the lower plate 1 is formed using a transparent insulating substrate such as glass. On the lower plate 1, a metal layer including molybdenum (Mo) is deposited by sputtering. A plurality of gate bus lines 20 extending in the horizontal direction and a plurality of gate electrodes 21 extending from the gate bus lines 20 are formed by patterning the molybdenum metal layer on the lower plate 1. A gate pad 22 is formed at a start end of each gate bus line 20 for connection to the output of the scan driver IC generating the scan signal of the picture.
As shown in FIGS. 2a-2c, the lower plate includes a gate insulation layer 23, such as SiNx, or SiOx disposed thereon. Such layer has a good adhesive property with an amorphous silicon and high insulating property.
On the gate insulation layer 23, an amorphous silicon (a-Si) or CdSe is deposited and patterned to form a semiconductor layer 13. On the semiconductor layer 13, an ohmic contact layer 14 is formed for providing a good ohmic contact between the semiconductor layer 13 and the source electrode 11 and the drain electrode 31.
On the entire surface of the lower plate 1 after the above mentioned processes have been completed, a metal layer including molybdenum, is deposited by sputtering and patterned to form a plurality of data bus lines 10 extending in the vertical direction as shown in FIG.1. Near the intersections of the gate bus lines 20 and the data bus lines 10, the source electrode 11 extends from the data bus line 10 and contacts one side of the ohmic contact layer 14, and the drain electrode 31 faces the source electrode 11 and contacts the other side of the ohmic contact layer 14. The data pad 12 is formed at the start end of each data bus line 10 for connection to the output of the signal driver IC generating the data signal of the picture supplied to the LCD.
After performing the above mentioned processing, a TFT switching element, which includes the gate electrode 21, the semiconductor layer 13, the source electrode 11 and the drain electrode 31, is formed.
Over the switching element, a passivation layer 40 is formed by depositing and/or coating an insulating layer including a Si bonding structure such as SiNx, SiOx, or BCB (Benzocycobutene), as shown in FIG. 2a. As shown in FIGS. 2b, 3b, and 4bafter coating a photo-resist 60 on the passivation layer 40 using a spin coating method, the photo-resist 60 is patterned by exposure using a mask. Here, the patterned photo-resist 60 covers the entire surface of the passivation layer 40 except surface portions covering the drain electrode 31, the gate pad 22 and the data pad 12.
As a result of etching the lower plate 1 including the patterned photo-resist 60 in the etching chamber using SF6+O2 or CF4+O2 as an etching gas to remove the uncovered portion of the passivation layer 40, a contact hole 50 is formed. Through the contact hole 50, a portion of the drain electrode 31 as shown in FIGS. 2b and 2c is exposed. The passivation layer 40 uncovered by the photo-resist 60 over the gate pad 22 and the data pad 12 is also etched by the etching gas such as SF6+O2 or CF4+O2 so that the pads 12 and 22 are exposed as shown in FIGS. 3b-3c and 4b-4c, respectively. All of the photo-resist 60 is removed by the etching gas, SF6+O2 or CF4+O2.
An ITO (Indium Tin Oxide) layer is deposited via sputtering on the entire surface of the passivation layer 40 having the contact hole 50. On the ITO layer, a photo-resist is coated via a spin coating method and is then patterned. By etching the lower plate 1 having the patterned photo-resist using an etching solution such as HCl, pixel electrodes and terminals contacting pads 12 and 22 are formed. After that, the remaining photo-resist on the lower plate 1 is removed using an organic solution including NMP (N-Methyl-Pyrrolidone), alcohol and amine.
Through the terminals, the gate pad 22 is connected to the output of the scan driver IC and the data pad 12 is connected to the output of the signal driver IC.
According to the conventional method for manufacturing the LCD as described above, the step of exposing the drain electrode 31 is explained below in greater detail with reference to FIGS. 2b and 2c. The etching process for the passivation layer 40 is performed by a chemical reaction in which the F radical of the SF6+O2 or CF4+O2 gas reacts with the Si4+ of the passivation layer 40 to form a volatile gas such as a SiF4. Therefore, the portions of the passivation layer 40 that are not covered by the photo-resist 60 react with the SF6+O2 or CF4+O2 gas to form a volatile SiF4 gas so that these portions are removed. However, a portion of the drain electrode 31 is also exposed as shown in FIG. 2b. Unfortunately, the molybdenum of the drain electrode 31 easily reacts with the SF6+O2 or CF4+O2 gas used for etching the passivation layer 40. Therefore, the exposed portion of the drain electrode 31 is damaged by etching when the passivation layer is etched, as shown in FIG. 2c. 
Referring to FIGS. 3a and 3b, the process for exposing the gate pad 22 is explained below in detail. As mentioned above, the portion of the passivation layer 40 located over the gate pad 22 is removed by the chemical reaction in which the SF6+O2 or CF4+O2 gas reacts with the passivation layer 40 to form a volatile gas such as a SiF4. Then, the gate insulating layer 23 including SiNx, or SiOx under the passivation layer 40 is removed by the same chemical reaction. Here, the gate pad 22 can be exposed to the SF6+O2 or CF4+O2 gas. As a result, the gate pad 22 including molybdenum is also easily damaged by the SF6+O2 or CF4+O2 gas, as shown in FIG. 3c. 
Referring to FIGS. 4a and 4b, the process for exposing the data pad 12 is explained below in detail. As mentioned above, the portion of the passivation layer 40 located over the data pad 12 is removed by the chemical reaction in which the SF6+O2 or CF4+O2 gas reacts with the passivation layer 40 to form a volatile gas such as a SiF4+, as shown in FIG. 4b. As a result, the data pad 12 is exposed to the SF6+O2 or CF4+O2 gas and the data pad 12 including molybdenum is easily damaged by the SF6+O2 or CF4+O2 gas, as shown in FIG. 4c. 
To overcome the problems described above, preferred embodiments of the present invention provide a method for etching a passivation layer while preventing any damage to an exposed metal layer.
According to a preferred embodiment of the present invention, a method for etching a passivation layer uses a CF4+H2 gas instead of the SF6+O2 or CF4+O2 gas used in conventional methods. As a result, preferred embodiments of the present invention provide an etching method in which a passivation layer 40 and a metal layer including molybdenum have different etching ratios relative to the etching gas including the CF4+H2 gas to thereby remove an insulation layer via the etching gas including an F radical and prevent damage from being caused to the exposed metal layer by the etching gas.
According to another preferred embodiment of the present invention, a method for manufacturing a lower plate of an LCD including a switching element having a gate electrode, a source electrode and a drain electrode, a data bus line connected to the source electrode of the switching element and a gate bus line connected to the gate electrode of the switching element includes the steps of forming a passivation layer covering the switching element, the gate bus line and the data bus line on the lower substrate, forming a patterning layer on the passivation layer via coating and patterning a photo-resist wherein the patterning layer has open portions exposing some portions of the passivation layer on the drain electrode, a start portion of the gate and data bus lines, removing the exposed portions of the passivation layer using an etching gas comprising CF4 and H2 gases, and removing the patterning layer on the passivation layer. In preferred embodiments of the present invention, a mixing ratio of the H2 gas to the CF4 gas is varied depending on the area of the portion of the passivation layer to be removed. In a specific preferred embodiment, the mixing ratio of the H2 gas to the CF4 is about 1% to about 20%.
According to preferred embodiments of the present invention, the passivation layer includes an insulating material having an Si bonding structure such as SiNx, SiOx or BCB. The gate and data bus lines, the gate, source and drain electrodes include at least one layer selected from a refractory metal such as Mo, Ta, Ti, MoSi, TaSi or TiSi and stacked metal layers including an aluminum layer and a layer made of the refractory metal.
According to preferred embodiments of the present invention, the etching gas for removing the exposed portions of the passivation layer further includes at least one of SF6+CHF3, CF4+CHF3, CF4+H2+He and CF4+H2+N2.
These and other elements, features, and advantages of the preferred embodiments of the present invention will be apparent from the following detailed description of the preferred embodiments of the present invention, as illustrated in the accompanying drawings.